1. Field of the Invention
The present invention relates to a voltage regulator and, more particularly, to a voltage regulator capable of stabilizing output voltages at load transients.
2. Description of the Prior Art
FIG. 1(A) is a circuit diagram showing a first example of a conventional linear regulator 11. The linear regulator 11 converts an input voltage Vin into an output voltage Vout, and supplies an output current Iout in accordance with a requirement of a load Id. A resistive voltage divider formed of series-connected resistors R1 and R2 generates a feedback voltage Vfb representative of the output voltage Vout. Through comparing the feedback voltage Vfb and a predetermined reference voltage Vref, an error amplifier 13 generates and applies an error voltage Verr to a gate electrode of a transistor PQ. The drain-source current channel of the transistor PQ is connected between the input voltage Vin and the output voltage Vout. As the error voltage Verr is applied to control the resistance of the drain-source current channel, the linear regulator 11 maintains the output voltage Vout at a regulated value and supplies the output current Iout in accordance with the requirement of the load Id. As shown in FIG. 1(B), which is a second example of a conventional linear regulator 12, an NMOS transistor NS may replace the PMOS transistor PQ and then function as a passive element between the input voltage Vin and the output voltage Vout. However in this case, the non-inverting input terminal of the error amplifier 13 is changed to receive the reference voltage Vref while the inverting input terminal is changed to receive the feedback voltage Vfb.
When the load Id makes a transient from heavy loading to light loading, e.g., the load Id is suddenly removed, an excessive portion of the output current Iout turns to charge the output capacitor Cout before the output current Iout eventually reduces to become equal to the light load Id in response to this transient. As a result, the output voltage Vout is raised out of the regulated value. In order to overcome this problem and suppress the overshooting of the output voltage Vout, the prior art suggests a current sinking circuit for providing the excessive portion of the output current Iout with a sinking path when the load transients occur.
In the first example of FIG. 1(A), the current sinking circuit 14a primarily includes a voltage comparator 15 and a switching transistor PS. When the load Id makes a transient from heavy loading to light loading and then causes the output voltage Vout to rise as mentioned earlier, the error amplifier 13 also correspondingly generates a rising error voltage Verr. Once the error voltage Verr reaches a predetermined trigger voltage Vtrg, the voltage comparator 15 turns on the switching transistor PS so as to form a sinking path for short-circuiting the output current Iout into the ground potential. In the second example of FIG. 1(B), the voltage comparator 15 of the current sinking circuit 14b is provided to compare the reference voltage Vref and the feedback voltage Vfb level-shifted by a predetermined offset voltage Vofs. When the feedback voltage Vfb becomes large enough to trigger the voltage comparator 15, the switching transistor NS is turned on so as to form a sinking path for short-circuiting the output current Iout into the ground potential.
Although the prior art of FIG. 1(A) or 1(B) uses the current sinking circuit 14a or 14b to provide the sinking path for suppressing the overshooting of output voltage Vout, the output current Iout is in fact dramatically pulled down since the switching transistor PS or NS when turned on short-circuits the output terminal of the linear regulator 11 or 12 directly to the ground potential. As an adverse result, the output voltage Vout is prone to oscillating at a high frequency and actually causes the current sinking circuit 14a or 14b to repeatedly turn the switching transistor PS or NS between on and off.